Apparatus for testing an electrical circuit for opens,shorts and cross connections with its terminal groups being sequentially connected to the apparatus



D. A. DEsLER Jan. 27, 1970i APPARATUS FOR TESTING AN ELECTRICAL CIRCUITFOR OPENS SHORTS AND CROSS CONNECTIONS WITH ITS TERMINAL GROUPS BEINGSEQUENTIALLY CONNECTED TO THE APPARATUS Filed DSC. 2, 1965 l5Sheets-Sheet 1 D. A. DEsLER 3,492,571 APPARATUS FOR TESTING ANELECTRICAL CIRCUIT FOR OPENS SHORTS Jan. 27, 1970 AND CROSS CONNECTIONSWITH ITS TERMINAL y GROUPS BEING SEQUENTIALLY CONNECTED TO THE APPARATUSJan. 27, 1970 Filed Dec. 2, 1965 D. A. DESLER APPARATUS FOR TESTING ANELECTRICAL CIRCUIT FOR OPENS SHORTS AND CROSS CONNECTIONS wITII ITSTERMINAL GROUPS BEING SEQUENTIALLY CONNECTED T0 THE APPARATUS 15Sheets-Sheet 3 l I GROLIJP I I PLUG OO|PLUG OI (so TERMSMSO TERMS) lGROUP 7 I PLUG I2, PLUG I3 l GROUP I3 PLUG 24 I PLUG 2S GROUP I9 I PLUG36 IPLUG 37 GROUP 2S PLUG 48 PLUG 49 PLUG 04|l PLUG O5 I PLUG IO PLUG I7I I PLUGZBI PLUG 29 I I l I 1 GROUP 2 GROUPS GROUP I4 GROUP 2O GROUP 26I PLUGOZIPLUG O3 PLUG I4|PLUG I5 PLUG ESIPLUG 27 PLUG38IPLUG 39 PLUG 50PLUGSI (SOTERMS)I(5OTERMS) I l I N I l I I GROUP 3 GROUP 9 GROUP I5 GROU'P 2| GROUP 27 PLUG 52 PLUG53 GROU'P Io GROUP 5 PLUG O8: PLUG O9 I II PLUG 20| PLUG 2| I PLUG32|PLUG 33 I I PLUG 44T PLUG 45 I GROUP 4 IGROUP I6 GROUP 22 GROUP 2a I L PLUG oeIPLUG o7 PLUG ISIPLUG I9PLUG3O|PLUG 3| PLUG 42|PLUG43 PLUG S4 PLUG'SS I `I I GROUP II GROUP I7GROUP 23 GROUP 29 PLUG 56 PLUG 57 I GROUP 6 GROUP I2 GROUP IS GROUP 24GROUP 3o I I PLUG Io| PLUG II PLUG 22IPLUG23 PLUG34I PLUG 3S PLUG46||PLUG 47 PLUG'SB PLUGSQ T l I (5p TERMS) (so TERMS) Tj P59) 7) F/G. 4ZZ O0 05 l0 I5 20 25 30 35 40 45 |00 O5 IO I5 20 25 30 35 40 45 III.IIIIIIIII II I I .2z-I F/G 5 TEST GIROUP I TEST PLUG I TEST PLUG TESTISHORTI OPEN UUAORANT w I QUAORANT x o TERMINALS So TERMINALS TENS TENSTENS I Q/Tf UN'TS IPI? ,2L/VITE? I IIIIIIIIIIIIIIIIIIII TERMINAL 9595@O4 09 I4 I9 24 29 34 3944 49|O4 O9 I4 I9 242934 39 4449 00 O5 I0 I5 2025 30 3.5 40 45OO O5 IO I5 2O 25 30 35 4Q 45 2/72/5IIIIIIIIIIIII'IIIIIIII PLUGSD Q Q Z/P 2//275 2/Po TEST GIROUP I1 /1 2m2m I z/Puo TEST PLUG Il TEST PLUG fZZ'E QUAORANT Y QUAORANT z 5oTERMINALS I 5o TERMINALS I I I IIIIIIIII III II O4 09 I4 I9 24 29 34 3944 49IO4 09 I4 I9 24 29 34 39 44 49 D. A. DESLER AND CROSS CONNECTIONSWITH ITS TERMINAL GROUPS BEING SEQUENTIALLY CONNECTED TO THE APPARATUSFiled Dec. 2, 1965 S HORTS 15 Sheets-Sheet 4 320/ 27 START CONTROL 48 m.4o-:MF I

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APPARATUS FOR TESTING AN ELECTRICAL CIRCUIT FOR OPENS, SHORTS AND CROSSCONNECTIONS WITH ITS TERMINAL GROUPS BEING SEQUENTIALLY CONNECTED TO THEAPPARATUS Filed Dec. 2, 1965 13 Sheets-Sheet '7 Jan. 27, 1970 n. A.DEsLER 3,492,571

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TO THE APPARATUS D. A. DESLER /56 -ZZ-BO APPARATUS FOR TESTI-NG ANELECTRICAL CIRCUIT FOR OPENS SHORTS AND CROSS CONNECTIONS WITH ITSTERMINAL GROUPS BEING SEQUENTIALLY CONNECTED O v x 1:5 sheets-sheet 15gef/P00 United States Patent O U.S. Cl. 324--73 13 Claims ABSTRACT F THEDISCLOSURE In apparatus for testing an electrical circuit forcontinuity, shorts and cross connections, terminals of the circuit aretested in groups, with the terminal groups being sequentially connectedto the apparatus in pairs. In testing a pair of the terminal groups, aseparate signal is applied to each of the terminals thereof insuccession and their other terminals are monitored to detect an error inthe electrical circuit. Detection of an error interrupts the testingoperation and energizes circuitry for indicating the terminals involvedand the nature of the defect.

This invention relates to apparatus for testing electrical circuitry,and more particularly to apparatus for testing electrical circuitrywhich is relatively extensive and complex in nature. It is an object ofthis invention to provide new and improved apparatus of this character.

In the manufacture of electrical circuitry having a plurality ofterminals which are interconnected by electrical conductors, such as aconnector plug type cable used in a telephone PBX (private branchexchange), it is standard practice to test the cable for continuity,including shorted, open and cross-connected terminals. Any wiring errorsare corrected as they are found, before incorporating the cable into thePBX.

Cable testing apparatus is known in which a signal is appliedsequentially to each terminal of a cable and at the same time is appliedto a corresponding terminal of a reference or control circuit, by meansincluding electromechanical stepping switches. While the signals arebeing applied to each cable terminal and its corresponding referencecircuit terminal, the signal outputs at the other cable terminals arecompared with the signal outputs at their corresponding referencecircuit terminals in sequence, by means of additional electromechanicalstepping switches and associated circuitry, to detect any wiring errorsin the cable.

The above described apparatus has various disadvantages and is notsuited for testing the cables of more recently developed PBX devices,the `wiring of which cables is relatively extensive and complex innature. For example, as a result of the cable and reference terminalsbeing compared in sequence, and the relatively slow operating times ofthe electromechanical switches, the apparatus has a relatively slowtesting rate. By way of illustration, the minimum time which would berequired to test a standard cable having three thousand interconnectedterminals utilizing test apparatus of this type, assuming that no errorsWere found in the cable, would be on the order of several hours. Inaddition, the test apparatus would have to be of such size andcomplexity as to make its use impractical.

In another known cable testing apparatus, which is tape programmed,input signals are applied sequentially to terminals of a cable and theapparatus checks for an output signal only at those terminals at whichan output signal should appear. While this apparatus provides a PatentedJan. 27, 1970 lCC reduction in cable test time as compared to theabovedescribed type of apparatus, it is of limited capacity, and wherethe wiring of the cable being tested is relatively extensive in nature,considerable manual connecting and disconnecting of terminals to andfrom the apparatus is involved, such that the cable test time still ison the order of one hour or more. Further, if this apparatus were madeof sucient size so as to eliminate this manual connecting anddisconnecting of the terminals, it would be of such size and complexityas to make its use impractical. This type of apparatus also isdisadvantageous because it primarily tests the cable for continuity, andmay not detect an error in which a terminal, While properly wired to oneor more other terminals, also is shorted to another terminal.

Accordingly, an object of this invention is to provide new and improvedapparatus which is particularly suited for the testing of electricalcircuitry which is relatively extensive and complex in nature.

Another object of this invention is to provide new and improvedapparatus for testing electrical circuitry which is relatively fastoperating as compared to prior known apparatus.

A further object of this invention is to provide new and improvedapparatus for testing electrical circuitry which is relatively small insize in comparison to prior known apparatus having a correspondingtesting capacity.

A still further object of this invention is to provide new and improvedapparatus for testing electrical circuitry in which manual connectingand disconnecting of terminals of the circuitry to and from theapparatus, other than at the beginning and end of a test operation, iseliminated.

A still further object of this invention is to provide new and improvedapparatus for testing electrical circuitry having sets of terminalswhich are interconnected by electrical conductors, wherein the apparatusdetermines the terminals involved in an error in the electricalcircuitry, including the set of terminals 'in which each of the involvedterminals is located.

In accordance with the invention, in apparatus for testing an electricalcircuit having a plurality of terminals which are interconnected byelectrical conductors, a signal is applied sequentially to each of theterminals and at the same time a signal is applied to a correspondingterminal of a control circuit, so that the signals feed into theelectrical and control circuits. An error in the electrical circuit thenis detected by simultaneously comparing the signal outputs at the otherterminals with the signal outputs at their corresponding referenceterminals.

In a preferred embodiment of the invention, apparatus for testing anelectrical circuit having sets of terminals which are interconnected byelectrical conductors includes rst control means for sequentiallyconnecting groups of the terminals and corresponding groups of terminalsof a reference circuit to the apparatus as first electrical circuit andreference circuit and reference circuit test groups, respectively. Wheneach of the electrical circuit terminal groups and its correspondingreference circuit terminal group are connected to the apparatus as theiirst test groups, a second control means sequentially connects selectedones of the other electrical circuit and reference circuit terminalgroups to the apparatus as second test groups, the second control meansbeing connected to energize the rst control means after the selectedother terminal groups have been connected to the apparatus, so that therst control means connects the next succeeding pair of terminal groupsto the apparatus as the first test groups. While each of the two pairsof electrical circuit and reference circuit terminal groups areconnected to the apparatus, a signal is sequentially applied to each ofthe electrical circuit terminals, and at the same time a signal isapplied to the corresponding reference circuit terminal, so that thesignals feed into the electrical circuit and the reference circuit,respectively. The electrical circuit then is checked by comparing thesignal output at each of the other terminals of the two electricalcircuit terminal groups, with the signal out put at the correspondingreference circuit terminal, to detect any disparity in the signaloutputs of the corresponding terminals as a result of an error. When anerror is detected the apparatus determines whether the error is causedlby shorted, open or cross-connected terminals, and also determines theterminals involved in the error, including the set of terminals in whicheach terminal is located.

This invention, together with further objects and advantages thereof,will best be understood by reference to the following detaileddescription taken in connection with the accompanying drawings, inwhich:

FIG. 1 illustrates the relative relationship of FIGS. 2A and 2B;

FIG. 2A is a block diagram of a portion of the apparatus;

FIG. 21B is a block diagram of the remainder of the apparatus;

FIG. 3 is a schematic representation of a PBX cable;

FIG. 4 is a schematic representation of cable connecting terminals ofthe apparatus as shown in FIG. 2A, which illustrates the manner in whichterminals of the PBX cable represented in FIG. 3 are connected to theapparatus as test groups for test purposes;

FIG. 5 shows a read-out display of the apparatus;

FIG. 6 is a detailed circuit diagram of parts of the apparatus as shownin the block diagram of FIG. 2A, including a start control circuit, apulse generator, a pulse gate and an associated delay circuit;

FIG. 7 is a detailed circuit diagram of a stepping circuit and a sendmatrix of the apparatus as shown in the block diagram of FIG. 2A;

FIG. 8A is a detailed circuit diagram of a part of a group controllercircuit of the apparatus as shown in the block diagram of FIG. 2A;

FIG. 8B is a detailed circuit diagram of another part of the groupcontroller circuit;

FIG. 9 is a detailed circuit diagram of error detect circuitry of theapparatus as shown in the block diagram of FIG. 2A, illustrating themanner in which a Wiring error in the cable represented in FIG. 3 isdetected, and also showing a digit grouping circuit of the apparatus asshown in the block diagram of FIG. 2B;

FIG. 10 is a detailed circuit diagram of a digit information collectingcircuit and one of a plurality of information transfer circuits of theapparatus as shown in the block diagram of FIG. 2B;

FIGS. 11A, 11B and 11E are detailed circuit diagrams of parts of aread-out cycle control circuit of the apparatus as shown in the blockdiagram of FIG. 2B;

FIGS. 11C and 11D show a diagram and a chart, respectively, illustratingan operating cycle for the part of the read-out cycle control circuitshown in FIG. 11A;

FIG. 12 is a detailed circuit diagram of a memory circuit and associatedinformation steering contacts of the apparatus as shown in the blockdiagram of FIG. 2B;

FIG. 12 is a detailed circuit diagram of a cable test plug quadrantdetector and a cable plug number pretranslator of the apparatus as shownin the block diagram of FIG. 2B, and

FIGS. 14A, B and C are detailed circuit diagrams illustrating a cableplug translator of the apparatus as shown in the block diagram of FIG.2B.

The illustrated embodiment of the invention is designed to test a PBXcable for continuity, including shorted, open and cross-connectedterminals. More specifically, the apparatus is designed to test a PBXcable C, as illustrated in FIG. 3, which includes Sixty terminal plugsP-00 through P-59, each having lifty terminals T for a total of threethousand terminals. Each of the terminals T, which in the illustratedembodiment of the invention are assigned the numbers 00 through 49, asshown in FIG. 4, is wired to one or more selected other terminals bysuitable conductor wires. The cable C is connected into a PBX apparatusby plugging the cable plugs Pe00 through P-59 to respective fixed plugsof the apparatus, and the cable is connected to the subject testapparatus by inserting the plugs into suitable receptacles (not shown)having terminals Which are connectible to the test apparatus in a mannerto be described.

In the event of an error in the cable C, the apparatus indicates thenumber of the plug P-00 through P-59 and the number of the terminalT-00` through T-49 under test, that is, the input terminal, when theerror is found and whether the error is a short, an open wire or a crossconnection. If the error is a short, the apparatus also indicates thenumber of the plug P-00 through Pe59 and the number of the terminal T-00through T-49 to which the test terminal is shorted, or if the fault isan open wire, the number of the plug and the number of the terminal towhich the test terminal should be connected. For this purpose, theapparatus includes a read out 21 in the form of a nixie lamp display, asillustrated in FIG. 5, which indicates the tens digit and the unitsdigit for the test plug number P-00 through P-59, the tens and the unitsdigits for the test terminal T-00 through T-49, etc., for a total oftwelve digits or pieces of information which are provided by theapparatus. A reading on the read-out display 21 of both a shortedterminal T00 through T-49 and an open terminal, is an indicated that across connection exists in the cable C.

With respect to the cable terminals T-00 through T-49 and the cableplugs P-tl() through P-S9, various abbreviations -used on the drawings,as for example in FIG. 5 for read-out lamps ZITUT, 21TUS, etc., of theread-out 21, and in the following description are defined as follows:TUT designates Terminal Units Test, that is, the units digit of theterminal under test (input terminal) when an error is found; TUSdesignates Terminal Units Short, the units digit of a terminal to whichthe test terminal is shorted; TUO designates Terminal Units Open, theunits digit of a terminal to which the test terminal should be connectedbut is not, and with respect to which the test terminal thus is open;PUT designates Plug Units Test, the units digit of the plug in which theinput terminal is located; PUS designates Plug Units Short, the unitsdigit of a plug having a shorted terminal; and PUO designates Plug UnitsOpen, the units digit of a plug having an open terminal. Similarly, TITdesignates Terminal Tens (digit) Test; TTS designates Terminal TensShort; TTO designates Terminal Tens Open; PTT designates Plug Tens Test;PTS designates Plug Tens Short, and PTO designates Plug Tens Open.

The illustrated embodiment of the invention operates upon the principleof comparing the cable C under test with a control reference circuit,hereinafter referred to as the program P (FIG. 2A), which is wired inthe manner that the cable should be wired. Preferably, the program P ismade up of removable circuit boards in a manner well known to thoseskilled in the art, to facilitate changing of the program for thetesting of other cables or electrical wiring.

The three thousand terminals T of the cable C are connected to theapparatus for test purposes in groups, rather than simultaneously, so asto reduce the size of the apparatus required. Accordingly, in theillustrated embodiment of the invention, as is shown in FIG. 3, thecable C is divided into thirty terminal groups C1-C30 with each groupincluding two of the plugs P-00 through P-59, or one hundred of theterminals T.

Two of the terminal groups C1-C30 (four plugs or two hundred terminals)are connected to the apparatus at any one time through two hundred cableconnecting terminals 22 (FIGS. 2A, 4 and 9). More specifically,referring to FIG. 4, it is seen that the two hundred cable connectingterminals 22 are divided into two groups of one hundred terminals each,one of the groups being designated as test group I or 22-1 and the othergroup of terminals being designated as test group II or 22-II. Each ofthe test groups 22-I and 22-II further is divided into two sets of fiftyterminals, with the resulting sets being designated as test plugquadrants W, X, Y and Z, and with the terminals of each quadrant havingassigned numbers 00 through 49.

Each of the cable terminal groups C1-C30 is connectible to the onehundred cable connecting terminals 22-1 and to the one hundred cableconnecting terminals 22-II. When one of the cable terminal groups C1-C30is connected to the cable connecting terminals 22-I, the terminals T ofone cable plug of the group are connected to respective ones of thecable connecting terminals in test plug quadrant W, and the terminals ofthe other plug of the group are connected to respective ones of thecable connecting terminals in test plug quadrant X. Similarly, when thesame cable terminal group is connected to the cable connecting terminals22-II, the terminals T of the groups plugs are connected to respectiveones of the cable connecting terminals of test plug quadrants Y and Z,respectively. Thus, the test plug quadrants W, X, Y and Z of the cableconnecting terminals 22 are representative of respective ones of thefour of the cable plugs P-00 through P-59 which are connected to thetesting portion of the apparatus at any one time.

The program P also is divided into thirty plug terminal groups P1-P30,as indicated in FIG. 2A, which are identical to the cable terminalgroups C1-C30 shown in FIG. 3. When two of the cable terminal groupsC1-C30 are connected to the apparatus for test purposes, the twocorresponding ones of the program terminal groups P1-P30 also areconnected to the apparatus as described in the preceding paragraph,through two hundred program connecting terminals 23, which are dividedinto test groups I and II in the same manner as the connecting terminals22 shown in FIG. 4. The connection of the cable terminal groups C1-C30and their corresponding program terminal groups P1-P30 to the apparatusin pairs is accomplished sequentially by a terminal group controller 24(FIGS. 2A and 8), which subsequently is described in greater detail.

START CONTROL CIRCUIT (FIGS. 2A and 6) Referring to FIGS. 2A and 6, itis seen that a start control circuit 26 is provided for initiatingoperation of the apparatus. After the cable plugs P-00 through P-59 0fthe cable C have been inserted into the above-mentioned receptacles, astart button 27 is depressed to energize a start relay 28 from asuitable voltage source of a power supply 29, the voltage source in theillustrated embodiment of the invention being shown in FIG. 6 as havinga magnitude of -48 v. The start relay 28 closes a contact 2SC-1 toenergize a hold relay 31 which locks operated and closes a contact 31Cto condition a lock-out relay 32 for operation.

When the start button 27 is released, the start relay 28 is deenergizedto release a contact 2SC-2 to its normally closed position to causeenergization of the conditioned lock-out relay 32. The lock-out relay 32then opens a contact 32C-1 in the energizing circuit of the start relay28 to prevent energization of the start relay during the test operationas a result of inadvertent pressing of the start button 27. The lock-outrelay 32 also cl-oses a contact 32C-2 to energize a delay relay 33; acontact 32C-3 to condition a test relay 34 for operation; a contact32C-4 to condition read-out control circuitry (subsequently to bedescribed) for operation; contacts 32C-5 and 32C-'6 to apply battery toelectronic circuits (subsequently to be described) from suitable voltagesources of the power supply 29, the voltage sources in the illustratedembodiment of the invention being shown in FIG. 6 as having magnitudesof -12 v. and -il.5 v., respectively; and a gate closing Contact 32C-7in a pulse gate 36.

The delay relay 33 opens a contact 33C-1 to remove battery from a memory37 (FIG. 2B), to restore the memory to a neutral condition and to causeit to forget any previously stored information. The delay relay 33 alsocloses a contact 33C-2 to energize a counter zero set relay 38, andcloses a gate closing contact 33C-3 in the pulse gate 36.

The counter zero set relay 38 closes a contact 38C-1 to cause a voltagepulse to be fed from the -48 v. voltage source of the power supply 29 toreset inputs of al1 electronic counters of the apparatus, to reset theirout puts to a zero state. The zero set relay 38 also closes a contact38C-2 to cause energization of the conditioned test relay 34, whichlocks operated. In addition the zero set relay 38 closes a gate closingcontact 38C-3 inthe pulse gate 36.

The energized test relay 34 opens a contact 34C-1 to deenergize thedelay relay 33, and also opens a gate closing contact 34C-2 in the pulsegate 36. The deenergized delay relay 33 then releases the contact 33C-1to its normally closed position to restore power to the memory 37,releases the contact 33C-2 to its normally open position to deenergizethe counter zero set relay 38, and releases the gate closing contact33C-3 in the pulse gate 36. When the counter zero set relay 38 isdeenergized it releases the normally open counter reset contact 38C-1and the normally open test relay energizing contact 38C- 2. The relay 38also releases the normally open contact SSC-3 in the pulse gate 36,thereby opening the gate and permitting pulses to flow from a pulsegenerator 39 through the gate t0 a stepping circuit 41 (FIG. 2A).

VUpon completion of the testing of the cableC or'the completion of theread out of an error, a release relay 42 (FIG. 6) is energized to open aContact in the energizing circuit of the hold relay 31, thereby droppingout the hold relay, and thus the lock-out relay 32 and the test relay34, to deenergize the apparatus.

PULSE 4GENERATOR The pulse generator 39 may be of any suitable type, andin the illustrated embodiment of the invention is shown in FIG. 6 asincluding a unijunction transistor relaXation oscillator 43, whichproduces a negative going output voltage pulse. The output pulsefrequency of the oscillator 43, and thus the testing rate if theapparatus, is determined by a series RC circuit 44 in a Well-knownmanner. The negative going pulses from the oscillator 43 are coupled bya suitable coupling capacitor to a NOR amplifiier `46, which causes aphase reversal of the pulses to make them positive going, and thesepositive going pulses then feed to the input of the pulse gate 36.

PULSE GATE (FIGS. 2A and 6) The pluse gate 36, which is normally open topermit the flow of pulses from the pulse generator 39 to the steppingcircuit 41 (FIGS. 2A and 7), is closed to preclude passage of pulsestherethrough by the start control circuit 26, as described hereinabove,and also by a signal from an error detect gate circuit 47 (FIG. 2B), ora signal from the group controller 24 (FIG. 2A), as will subsequently bedescribed in greater detail. The pulse gate 36 includes a pair of seriesconnected NOR ampliers 48 and 49, with the output of the amplifier 49being connected to the input of the stepping circuit 41.

STEPPING CIRCUIT (FIGS. 2A and 7) As the stepping circuit 41 isenergized in response to the pulses from the pulse gate 36, itcooperates With an associated two hundred cross point send matrix 51 tocause signals to be applied sequentially to the two hundred cableconnecting terminals 22, and thus sequentially to the terminals T of thetwol of the cable terminal groups C1 C30 which are connected thereto atany one time. As a signal is applied to each cable connecting terminal22, it also is applied to the corresponding program connecting terminal23, and thus to the program terminal which is connected to the programconnecting terminal at that time.

The stepping circuit 41 includes a units digit binary counter 52 and atens digit `binary counter 53. As is shown in detail in FIG. 7, thecounters 52 and 53 are in the form of nine saturated Hip-flop circuitsarranged in a simple series string. The units counter 52 includes fourof the flip-flops (UNITS FF1-FF4) and has a basic count of sixteen, onlyten of which (one for each units digit) are required for testing thecable C, while the tens counter '53 includes five of the flip-flop (tensPF1-FFS) and has a basic count of thirty-two, only twenty of which (onefor every ten terminals) are required for testing the cable as shown inthe illustrated embodiment of the invention.

Accordingly, to reduce the test set cycle time, the count of each of thecounters 52 and 53 may be reduced by feeding lback a signal from oneip-op of the counter to a preceding flip-op, in a well-known manner, ifdesired. For example, the basic count of the tens counter 53 may beconverted from thirty-two to a basic count of twenty-four, twenty of thedigits being used for the actual testing of the cable C and theremaining extra four digits being used for self-testing if theapparatus, or being available for other purposes, such as the testing ofselected terminals of an electrical circuit, as set forth at the end ofthis description. The basic count of the units counter 52 may be reducedin a similar manner.

The outputs of the tiipdlops of the units counter 52 are connected tobinary to decimal converters 56-0` through 56-9 in the form of positiveAND gates so as to energize the gates sequentially in a manner wellknown to those skilled in the art. The positive output pulse or signalfrom each of the energized AND gates 56-0 through 56-9 is amplified andinverted by a units digit send matrix driver 57 in the form of a NORamplifier, and then is applied to respective ones of two hundred crosspoints 58-00 through 58-199 of the send matrix 51. Similarly, the outputsignals of the ip-ops of the tens counter 53 energize binary to ydecimalconverters 59-0 through 59-19 sequentially, and the output signal ofeach of these converters is amplified by a send matrix driver 61 andthen is applied to respective ones of the cross points 58-00 through58-199 of the send matrix 5-1. Where digit counts of the counters 52 and53 are used for self-testing of the apparatus, or for other purposes,additional ones of the binary to decimal converters 516 and 59 may beprovided, as necessary. The last flip-flop (TENS FFS) of the tenscounter 53 also is connected to feed a pulse to the group controller 24as the tens counter completes each counting cycle, that is, as thestepping circuit 41 Completes each sweep through the send matrix `51.

SEND MATRIX (FIGS. 2A AND 7) Each of the two hundred cross points 58-00`through 58-199 of the send matrix 51 is a negative AND gate, at bothinputs of which a negative potential must be present before a negativepotential is produced at its output, and each AND gate is wired to applysignal, when energized, to an associated pair of the cable and programconnecting terminals 22 and 23. As is illustrated in FIG. 7, the unitsand tens send matrix drivers 57 and 61 are wired to the AND gates 58-00through 58-199 such that only one of the AND gates will receive anegative potential from both a units driver and a tens driver at any onetime, and thus a signal is produced at the output of only one of the ANDgates at any one time.

GROUP CONTROLLER (FIGS. 2A, 8A AND 8B) Referring to FIG. 2A, it is seenthat the group controller 24 for sequentially connecting the cableterminal groups C1-C30 to the apparatus in pairs, and for simultaneouslyconnecting the corresponding ones of the program terminal groups P1-P30to the apparatus, includes a -rst binary counter 62 for connecting eachcable terminal group and the corresponding program terminal group to theapparatus as test group I terminals. A second binary counter 63 isprovided for connecting the cable and program terminal groups Cl-C30 andP1P30 to the apparatus as test group II terminals. In this regard, thegroup control counters 62 and 63 control relay trees -64 and 66,respectively, and each of the relay trees have output leads 64a and 66awired to cable group connecting relays 67-1 and 67-II, respectively, forconnecting the cable terminal groups C1-C30 to the cable connectingterminals 22-1 and 22-II, and also wired to program group connectingrelays 68-1 and 68-II, respectively, for connecting the program terminalgroups P1-P30 to the program connecting terminals 23-I and 23-II.

More specifically, referring to FIG. 8A, it is seen that the counters 62and 63 are in the form of Hip-Hop circuits in a simple series array,with the rst ip-llop of the test group I control counter 62 receivinginput pulses from the last flip-flop of the test group II controlcounter 63. As noted hereinabove, the counter 63 receives input pulsesfrom the output of the tens binary counter 53 of the send matrixstepping circuit 41, and thus, for each sweep of the stepping circuitthrough the cross points 58-00 through 58-199 of the send matrix 51, aninput pulse is received by the counter 63.

As the counter 63 receives input pulses from the send matrix steppingcircuit 41, the ip-ops of the counter are energized to energizerespective control relays 69-1 through 69-5. Referring to FIG. 8B, it isseen that as the relays 69-1 through 69-5 are energized they closerespective contacts 69C-1 through 69C-5 to energize respective relays7141 through 715 of the relay tree 66. The relays 71-1 through 715control contacts in the relay tree Z6 in a well-known manner, tocomplete electrical paths through the relay tree to its output leads66a-0 through 66a-31 in sequence, thereby sequentially actuating thecable group connecting relays 67-II-1 through 67-II-30 and theircorresponding program group connecting relays 68-II-1 through 68-II-30,and thus connecting the cable and program terminal groups C1-C30 andP1*P30 to the apparatus as test group II terminals for test purposes.

A portion of each input pulse to the counter 63 energizes a count delaygenerator 72 (FIGS. 2A and 8A) of the group controller 24, in the formof a monostable multivibrator. The generator 72 feeds a pulse back tothe pulse gate 36 (FIGS. 2A and 6) to close the gate temporarily, so asto permit time for the above-described relays 67, 68, 69 and 71, as wellas relays (subsequently to be described) of the counter 62 and the relaytree 64, to open and close their respective contacts, and for transientconditions as a result of this relay action to die out, before the nextcounting cycle of the stepping circuit begins.

As the counter 63 completes each of its counting cycles, one portion ofthe output pulse from its last flip-Hop is applied to a count transfercontrol 73 in the form of two series connected one-shot multivibrators,for a purpose subsequently to be described, and the other portion of thepulse is applied to the rst flip-flop of the counter 62, as noted above.Thus, for each complete counting cycle of the counter 63, the counter 62is advanced one count.

As the counter 62 proceeds through its counting cycles in response toinput pulses from the counter 63, it causes each of the cable terminalgroups C1-C30 and its corresponding one of the program terminal groupsP1-P30 to be connected to the apparatus as test groups I terminals (FIG.4), by means of group control relays 74-1 through 74-5 and the relaytree 64 (FIG. 2A), in the same manner as described above with respect tothe counter 63 for the test group II terminals. In this regard, therelay tree 64, which is not shown in detail in the drawing since it issubstantially identical in construction and operation to the relay tree66 (FIG. 8B), includes contacts which correspond to the contacts 69C-1through 69C-5 and t 9 which are closed by the relays 741 through 74-5,to energize relays which correspond to the relays 71-1 through 71-5 andwhich control respective contacts in the relay tree 64 to energizesequentially the cable and program group connecting relays 67-1 and 68-1(FIG. 2A).

From the foregoing description, it is seen that when the steppingcircuit 41 makes its initial sweep through the send matrix 51, none ofthe cable and program terminal groups C1-C30 and P1-P30 have yetbeenconnected to the apparatus by the group controller 24. Instead, theapparatus tests itself to insure that signals are Vbeing fed from thesend matrix 51, this being accomplished by error detect series 76 (FIGS.2A and 9) subsequently to be described.

After the stepping circuit 41 completes its initial sweep through thesend matrix 51, the output pulse from the tens binary counter 53 isapplied to the counter 63 to raise it one count. The stepping circuit 41then sweeps through the send matrix 51 again, whereupon the counter 63is raised to its next count to energize the relays 67-II-1 and 68-II41,thereby causing the rst of the cable terminal groups C1 and itscorresponding program terminal group P1 to be connected to the apparatusas test group II terminals. This sequence of operation is continueduntil all thirty cable terminal groups C1C30 and their correspondingprogram terminal groups P1-P30 have been connected to the apparatus.During this initial counting cycle, the counter 62 has not yet beenactuated to connect any of the terminal groups C1-C30 and P1- P30 to theapparatus as test group I terminals.

After the counter 63 completes its rst counting cycle the output pulsefrom its last flip-flop is applied to the counter 62 to raise it onecount, whereupon the apparatus proceeds through another counting cycleof the counter 63. When the next output pulse from the last stage of thecounter 63 is applied to the counter 62, the counter 62 causes cable andprogram terminal groups C1 and P1 to be connected to the apparatus astest group I terminals. Up to this time the apparatus has been testingitself, and for shorts within the individual plugs P- through P-59.

When the counter 63 receives its next input pulse from the send matrixstepping circuit 41, the counter causes cable and program terminalgroups C2 and P2\ to be' connected to the -apparatus as test group IIterminals. Now, :as the stepping circuit 41 sweeps through the sendmatrix '51, the cable Iwiring between the cable terminal groups C1 andC2 is checked by the error detect circuits 76. When the stepping circuit41 completes this sweep cycle the output pulse from the tens binarycounter 53 to the counter 63 causes cable and program terminal groups C3and P3 to be connected to the apparatus a-s test group II terminals, andthe cable wiring between the cable terminal groups C1 and C3 is checkedby the error detect circuits 76. This procedure continues until allsubsequent cable terminal groups C4-C30 have been connected to theapparatus and checked with respect to cable terminal group C1, whereuponthe counter 62 again is actuated from the counter 63 to connect cableand terminal groups C2 and P2 to the apparatus as test group Iterminals. Cable terminal group C2 then is checked with respect tosubsequent cable terminal groups (3S-C30', with the cable and programterminal groups C2 and P2 as the test group I terminals. This testingprocedure continues until all of the cable terminal groups C1C30` havebeen connected to the apparatus by the operation of the counter 62 andtested as test group I terminals.

Referring to FIG. 8B, it is seen that the leads 66a-0 and 66a-31 areopen and not connected to any other circuitry of the apparatus.Similarly, the lead of the relay tree 64 (not shown in detail)corresponding to the lead 66a-0 is open; however, the lead of the relaytree 64 corresponding to the lead 66a-31 is connected to the releaserelay 42 (FIG. 6), for energizing the relay and shutting off theapparatus, as above described, upon the completion of the testoperation.

As noted hereinabove, each of the cable terminal groups C1-C30 is testedas test group I terminals against only the cable terminal groupssubsequent thereto. In this regard, if the test group II control counter63 began each counting cycle at its lowest count, all of the groupsC1-C30 would be tested twice, thereby doubling the test time. To obviatethis, the group controller 24 is arranged so that the counter 63 beginseach counting cycle at a count which is one unit above the startingcount of its preceding cycle.

For this purpose, the output of each ip-flop stage of the test group Icontrol counter 62 is connected to a irst leg of an associated counttransfer gate in the form of an AND gate 77, and the output of each ANDgate is connected to the corresponding Hip-flop stage in the counter 63.Further, the output of the count transfer control 73 is connected tosecond legs of the AND gates 77 by a lead 78.

In the illustrated embodiment of the invention, the counter 63 beginsits rst counting cycle with a first count which is arbitrarilydesignated zero, and the final output pulse from the counter splits toenergize the counter 62, to advance it to a rst count of zero, and toenergize the count transfer control 73. The count transfer control 73then feeds a delayed pulse to each of the AND gates 77, and this pulsecombines with a pulse from the energized rst flip-flop stage of thecounter 62 to energize the AND gate to lwhich this stage is connected.The energized AND gate 77, rwhich can energize any or all of theflip-flop stages vin the counter 63, then energizes therst stage,thereby setting this counter at the same binary count -as the counter62, that is, a count of zero. In the transfer of the count of thecounter 62 to the counter 63 upon the completion of the subsequentcounting cycles of the counter 63, the delayed pulse from the counttransfer control 73 combines with one or more pulses from the flip-dopstages of the counter 62, depending upon which stages are energized.Thus, as the counter 63 receives its first input pulse from the steppingcircuit tens binary counter 53, at the beginning of its second countingcycle, the counter is stepped immediately to its second count of one, atthe start of its third counting cycle it will be stepped immediately toa count of two, etc.

ERROR DETECT CIRCUITS (FIGS. 2A and 9) Associated with each of the onehundred pairs of cable and program connecting terminals 22-I and 234,and the cross point 58 of the send matrix 51 from which the terminals ofthe pair receive their input signals, is one of the above-mentionederror detect or compare circuits 76, one of which, for the cross point58-10, is shown in detail in FIG. 9 and designated 76-I. Similarly,associated with each of the one hundred pairs of cable and programconnecting terminals 22-II and 23-II and its respective cross point 58is another one of the compare circuits 76, one of which, for the crosspoint 58-190, also is shown in detail in FIG. 9 and designated 76-II.Inasmuch as all of the compare circuits 76-I are identical, and :all ofthe compare circuits 'I6-II are identical, only the two circuits shownin FIG. 9 will be described.

The compare circuits 76-I and 76-II in FIG. 9 are connected to theirrespective cable connecting terminals 22-1 and 22-II by leads 79-I and79-II, and to their respective program connecting terminals 23-I and23-II by leads 81-1 and 81-II. The cable connecting terminal 22-I isconnected to a respective one of one hundred leads 82 (only one shown),:and each of the thirty cable terminals T (one from each of the cableterminal groups C1-C30, with two being shown in FIG. 9 and designated acable input terminal Tai and a cable output terminal Tco) which receivessignals from and passes signals to the connecting terminal, isconnectible to the lead `82 through a normally open contact 67-IClocated in a lead 83 and closed by a respective one of the thirty cableconnecting 11 relays 67-I as described hereinabove. Similarly, the cableconnecting terminal 22-II is connected to a lead 84 and each of thethirty cable terminals T which receives signals from and passes signalsto this connecting terminal is connectible to the lead 84 by a normallyopen contact 67-IIC located in a lead 86 and closed by a respective oneof the thirty cable connecting relays 67-II. The corresponding terminalsof the program terminal groups P1-P30 vare connectible to the programconnecting terminals 23-I and 23a-II in the same manner by circuitryincluding contacts controlled by respective ones of the programconnecting relays 68-I and 68-II.

As shown in FIG. 9, the compare circuit 76-I illustrates the function ofone of the compare circuits when associated with the cable inputterminal Tcl, while the compare circuit 76-II illustrates the functionof one of the compare circuits when associated with the cable outputterminal Tw, with the terminals Tc, and Tco properly connected by acable wire Cw.

As each of the AN gates 58 of the send matrix 51, such as the gate 50-10shown in FIG. 9, is energized, its output signal feeds to a point 87-Iwhere the signal splits, with a portion of the signal feeding through asteering diode 88-1 to a point 89-1 where it again splits with a portionthen feeding to the cable connecting terminal 22-I by means of the lead7 9-I. The other portion of the output signal feeds through a secondsteering diode 88-2 to a point 91-I Where it again splits, with aportion then feeding to the program connecting terminal 23-1 by means ofthe lead 81-1. At the points 89-1 and 91-1, the other signal portionsfeed into the compare circuit 76-I and the compare circuit verifies thatthe send matrix output signal was received at both points.

From the program connecting terminal 23-1 the signal portion feeds to aprogram input terminal Tpi, through a program wire PW to a programoutput terminal Tpo, to the program connecting terminal 23-II, and thento the compare circuit 76-II along the lead 81-II to a point 91II.Similarly, the signal portion at the cable input connecting terminal22-I feeds to the cable input terminal Tci, through the cable Wire CW tothe cable output terminal Tco, to the cable connecting terminal 22-II,and then to the compare circuit 7 6-II along the lead 79-II to a point89-II.

Each compare circuit 76(I or II) includes four NOR amplifiers 92, 93, 94and 96, the amplifiers 94 and 96 being output amplifiers and having.output leads 97 and 98, respectively. The amplifiers 92, 93, 94 and 96are wired, as illustrated in FIG. 9, such that if the compare circuit 76(-I or II) receives a signal at both of its associated points 89 (-I orII) and 91 (-I or II), or receives no signal at either point, neither ofthe output amplifiers 94 and 96 is energized and no signal appears oneither of their output leads 97 and 9S.

Thus, in the operation of the compare circuit 76-I in FIG. 9, if signalsare received at both of the points 89-1 and 91-I, signal portions feedfrom the point 89-1 through steering diodes 88-3 and 88-4 into thecompare circuit, and from the point 91-1 through steering diodes 88-5and 88-6 into the compare circuit, whereby neither of the outputamplifiers 94 and 96 is energized and no signal appears on either oftheir output leads 97 and 98. However, if one of the points 89-I or 91-Ireceives no signal, one or the other of the output amplifiers 94 and 96will be energized to initiate a sequence of operations culminating inshut down of the apparatus, as will subsequently become apparent.

Similarly, in the operation of the compare circuit 76-II in FIG. 9, thesignals fed to the points 89-II and 91-II pass through diodes 88-3,88-4, 88-5, and 38-6 into the compare circuit 76-II, whereby neither ofits output amplifiers 94 and 96 is energized. At the same time, if thecable input terminal Tc, is not shorted to, or open with respect toanother terminal T of the cable C, none of the other compare circuits76-I and 76-II of the apparatus will be energized and the steppingcircuit 41 (FIG. 7) steps to the next send matrix cross point 58-11.

If the cable input terminal Tc, is improperly connected to the cableoutput terminal T.,o by the wire CW, or is shorted to the cable outputterminal rather than properly wired thereto, the program wire PW,instead of being connected to the cable output terminal Tpo as shown inFIG. 9, would be connected to a different program terminal. An outputsignal then is received from the cable output terminal Tco at the point89II when it should not be receiving a signal, but no signal is receivedat the program point 91-II, and thus the output amplifier 94 of thecompare circuit 76-II is energized to indicate a short.

Similarly, if the wire CW is broken, or instead of being properlyconnected to the cable output terminal Tco as shown in FIG. 9 isimproperly connected to a different terminal T of the cable C, an outputsignal from the program output terminal T1D0 is received at the programpoint 91-II, but no signal is received at the cable point 89-II, and theoutput amplifier 96 of the compare circuit 76-II is energized toindicate an open.

From FIG. 9, it is seen that as the stepping circuit 41 (FIG. 7)proceeds through the send matrix 51 beyond the cross point 58-10` andsubsequently applies a signal to the cross point 58-190, the signal willfeed to a point 87- II which corresponds to the point 87-1. It isapparent that portions of the signal then will flow into the comparecircuit 76-II, and in reverse directions through the cable and programwires CW and PW to the compare circuit 76-I, whereby the functions ofthe two compare circuits are reversed from that as above described.Thus, each Wire Cw of the cable C is tested twice by the apparatus as itproceeds through its normal cycle of operation.

UNITS AND TENS DIGIT GROUPING CIRCUIT (FIGS. 2B and 9) In connectionwith a units and tens digit grouping circuit 99 of the apparatus,reference is rst made to FIGS. 4 and 7 for the purpose of furtherillustrating the relationship between the two hundred cross points 58-00through 58-199 of the send matrix 51, the compare circuits 76-I and76-II, and the two hundred terminals T of four of the test plugs P-00through P-59 which are connected to the apparatus at any one time. Inthis regard, cross points 58-00 through 49 apply signals sequentially tothe cable connecting terminals 22-I-00 through 49 of the test plugquadrant W; cross points 58-50 through 99 apply signals sequentially tothe terminals 224-00 through 49 of the testplug quadrant X; cross points59- 100 through 149 apply signals sequentially to the terminals 22-II-0ythrough 49 of the test plug quadrant Y; and cross points 58-150 through199 apply signals sequentially to the terminals 22-II-00 through 49 ofthe test plug quadrant Z. Thus, by way of illustration, the cross point58-10 in FIG. 9 feeds input signals to the cable connecting terminal22-1-10 in test plug quadrant W (W-10), and thus to the terminal 10 ofthe plugs P-00 through P-59 which are connected to the apparatus in testplug quadrant W, and this cross points compare circuit 76-1 receivesoutput signals from these terminals. Similarly, the cross points 58-190in FIG. l9 feeds input signals to the cable connecting terminal 22-II-40in quadrant Z (Z-40), and thus to the terminal 40 of the plugs P-tlOthrough P-59 which are connected to the apparatus in test plug quadrantZ, and this cross points compare circuit 76II receives output signalsfroml these terminals.

Referring to FIG. 9, it is seen that the purpose of the units and tensdigit grouping circuit 99 is to collect short and open digit informationfrom the output ampliers 94 and and 96 of the compare circuits 76-I and76II. With respect to the test plug quadrant W, all cornpare circuitoutput amplifiers 94 (shorted terminal) for the cable connectingterminals 22-I having the same units digit feed to a respective one of aplurality of ten (one 13 for each of the units digits through 9) gatingcircuits 101W; all output amplifiers 96 (open terminal) for the cableconnecting terminals having the same units digit feed to a respectiveone 0f a plurality of ten gating circuits 102W; the amplifiers 94 forthe cable connecting terminals having the same tens digit feed to arespective one of a plurality of five gating circuits 103W; and theamplifiers 96 for the cable connecting terminals having the same tensdigit feed to a respective one of a plurality of five gating circuits104W. For example, the output amplifiers 94 for the terminals W-10through W-19, having the common tens digit 1, are all connected to thegating circuit 103W-1, and the output amplifiers 96 for these terminalsall are connected to the gating circuit 104W-1, as is illustrated inFIG. 9 by the output amplifiers 94 and 96 for the terminal W-10 (crosspoints 58-10). The output amplifiers 94 and 96 of the compare circuits76-I and 76-II for the cable connecting terminals 22-I and 22-II in thetest plug quadrants X, Y and Z are connected in the same manner togating circuits 101X, Y and Z, 102X, Y and Z, 103X, Y and Z and 104X, Yand Z.

When a malfunction in the apparatus or a fault in the cable C is foundby the compare circuits 76-1 and 76-II l such that one of the groupinggates 101W, X, Y and Z through 104W, X, Y and Z receives an input pulsefrom one of its assocated compare circuits, the output pulse of thegrouping gate energizes the error detect gate circuit 47 (FIG. 2B). Theoutput pulse of the error detect gate circuit 47 causes closing of thepulse gate 36, as noted hereinabove, causing the apparatus to lock onthe error.

More specifically, when any one of the units digit short grouping gates101W, X, Y and Z has a pulse applied thereto from one of its associatedcompare circuits 76, the output pulse of the grouping gate is applied toa gate 47a (FIG. 10) of the circuit 47. Similarly, the output pulse ofany one of the units digit open grouping gates 102W, X, Y and Z isapplied to a gate 47b, the output pulse of any one of the tens digitshort grouping gates 103W, X, Y and Z is applied to a gate 47C, and theoutput pulse of any one of the tens digit open grouping gates 104W, X, Yand Z is applied to a gate 47d. The gates 47a, b, c and d have theiroutputs connected to a common lead 107 which is connected to feed anoutput pulse from one of these gates to the pulse gate 36 (FIG. 6) toclose the gate by temporarily inhibiting the ow of pulses from the pulsegenerator 39 to the pulse gate. This output pulse also feeds by way ofthe lead 107 to energize a delay circuit 108 (FIG. 6).

After a predetermined time delay, a relay 109 of the delay circuit 108is energized and closes a contact 109C to energize a relay 111. Theenergized relay 111 closes a first contact 111C-1 in the pulse gate 36to lock the gate closed and also closes a contact 111C-2 to initiate areadout cycle, as will subsequently be described. In this regard,however, the time delay of the delay circuit 108 is such as to permittransient conditions in the apparatus to die out, whereby the comparecircuits 76-I and 76-II can verify that an error in the cable or amal-function in the apparatus is actually present, and that the initialinhibiting of the flow of pulses from the pulse generator 39 to thepulse gate 36 was not due to transient conditions. lf the initial pulseinhibiting was due to transient conditions, the relay 109 of the delaycircuit 108 does not become energized, and when the transient conditionshave dissipated, the pulses again will begin to flow from the pulsegenerator 39 through the pulse gate 36, Whereas if the inhibiting wasdue to an actual error, the relay 109 is energized to energize the relay111, which then locks the pulse gate closed and initiates the read-outcycle.

DIGIT INFORMATION COLLECTING CIRCUITS (FIGS. 2B AND l0) The groupinggates 101W, X, Y and Z through 104W, X, Y and Z of the digit groupingcircuit 99 are wired to the error detect gates 47a, b, c and d through adigit information collecting circuit 112, which also is designed tocombine units and tens digit information for the four test plugquadrants W, X, Y and Z. In this regard, as is shown in detail in FIG.10, the circuit 112 includes ten sets (one for each of the units digits0 through 9) of four gates 113W, X, Y and Z for collecting units digitshort information, and ten sets of four gates 114W, X, Y and Z forcollecting units digit open information. Thus, the four grouping gates101W, X, Y and Z (units digit short information) for each units digitare wired to respective ones of the collecting gates 113W, X, Y and Zfor that digits, and the four grouping gates 102W, X, Y and Z (unitsdigit open information) for each units digit are wired to respectiveones of the collecting gates 114W, X, Y and Z for that digit. Forexample, the four grouping gates 101W-0, 101X-0, 101Y-0 and 101Z-0 arewired to the collecting gates 113W, X, Y and Z, respectively, for theunits digit zero.

Each set of the units digit short information collecting gates 113W, X,Y and Z has a first normally open output lead 116 for connecting thegates to a first input of a respective one of ten information transfercircuits 117-0 through 1179-9 (only circuit 117-0 being shown), and asecond output lead 118 connected by a lead 119 to the input of the errordetect gate 47a. The sets of units digit open information collectinggates 114W, X, and Z are connectible to the information transfercircuits 117 by normally open output leads 121, and are connected by alead 122 to the error detect gate 47b n the same manner.

Similarly, the grouping gates 103W, X, Y and Z for tens digit shortinformation are wired to five sets of tens digit short informationcollecting gates 123W, X, Y and Z, the grouping gates 104W, X, Y and Zfor tens digit open information are wired to five sets of tens digitopen information collecting gates 124W, X, Y and Z, these collectinggates also being connectible to the information transfer circuits 117,and being connected to the error detect gates 47c and 47d, respectively.

INFORMATION TRANSFER CIRCUITS (FIGS. 2B AND 10) As noted hereinabove,the apparatus is designed to provide twelve digits or pieces ofinformation (FIG. 5), each of which could be any one of a plurality ofdigits, and which in the case of a units digit could be any one of tendigits O-9. Accordingly, to reduce the amount of wiring required and thesize of the apparatus, the apparatus is designed to transfer testinformation from the send matrix drivers 57 and 61 (FIGS. 2A and 7), thedigit information collecting circuit 112 (FIGS. 2B andlO), and from aplug number translator 126 (FIGS. 2B and 14), to the memory 37 (FIGS. 2Band l2) and ultimately to the read out 21 (FIGS. 2B, 5 and 12), one itemor digit at a time rather than simultaneously, by means of theinformation transfer circuits 117.

As is shown in FIG. l0 by the information transfer circuit 1170, each ofthe ten information transfer circuits 117-0 through 117-9 includessuitable signal amplifiers 117A, and a relay 117R which controls anassociated Contact for the purpose of transferring cable terminal digitinformation from the send matrix drivers 57 and 61 and the informationcollecting circuit 112 to the memory 37, in a manner to be described.Each of the information transfer circuits 117 also includes a normallyopen contact 111C-3, which is closed by the relay 111 of the delaycircuit 108 upon the apparatus detecting an error, as above described,to connect the information transfer circuit to a respective one of aplurality of input leads 3711-0 through 37a-9 (FIGS. 10 and l2) of thememory 37.

Associated with each of the information transfer circuits 117-0 through117-4 is a terminal tens test information collecting point 117P(left-hand side of FIG. l0) to which the tens matrix drivers 61 areWired by leads 61a through suitable diodes, which are not shown. More

